The disclosures of U.S. Pat. Nos. 4,541,046, 4,617,625 and 4,128,880 and S. Kawabe, et al., "The Single-Vector-Engine Supercomputer S-820 Delivers", Nikkei Electronics, Nikkei-McGraw-Hill, Inc., Dec. 28, 1987 are related to the present application and incorporated herein by reference.
The present invention relates to a system which is capable of executing a program described or a load module compiled on the assumption of two or more different instruction set architectures in a vector processor type supercomputer for scientific and technical calculations configured of a scalar processing unit for processing a scalar instruction and a vector processing unit for processing a vector instruction.
The vector processor type supercomputer is utilized for the purpose of performing high-speed scientific and technical calculations. The representative vector processors are CRAY-1 developed by Cray Research, Ltd., VP-200 developed by Fujitsu, Ltd., VP-2000 series developed by Fujitsu, Ltd., and S-810 developed by Hitachi, Ltd. Those techniques concerned with the supercomputer are described in the following publications.
CRAY-1 developed by Cray Research, Ltd. is disclosed in JP-A-61-131169.
S-810 developed by Hitachi, Ltd. is disclosed in U.S. Pat. Nos. 4,541,046 and 4,617,625.
S-820 developed by Hitachi, LTd. is disclosed in the S-820 article.
In the above-mentioned instruction set architectures of a vector processor, that is, a logical structure of a computer defined by an instruction set consisting of a scalar instruction and a vector instruction, a register arrangement, and an I/O instruction interrupt, the scalar instruction is defined as one provided in a general-purpose computer and the vector instruction is defined as one for rapidly processing the calculations of arrays frequently taking place in scientific and technical calculations. The vector processor is configured to have a scalar processing unit for processing scalar instructions (referred to as an SPU) and a vector processing unit for processing vector instructions (referred to as a VPU).
The SPU and the VPU work in concert to process one program at high speed. The instruction fetch by the SPU and VPU can be, in large, divided into two types.
(1) In the architecture of a scalar instruction/vector instruction mingled type, the SPU fetches a scalar instruction as well as a vector instruction. If the vector instruction is fetched, the instruction is sent to the VPU for executing it therein. This type of vector processor is the foregoing CRAY-1, VP-200 or VP-2000 series, the latter two of which are developed by Fujitsu, Ltd.
(2) In the architecture of a scalar instruction/vector instruction separate type, when the SPU fetches an instruction for starting the vector processing and decodes it, the VPU is started. This type of vector processor is the foregoing S-810 or S-820 developed by Hitachi, Ltd. When the instruction for starting the CPU (an Execute Vector Processing Instruction, for short, an EXVP instruction as in S-810 or S-820) is decoded by the SPU, the information containing a location of a vector instruction stream specified as an operand of the instruction is sent to the VPU together with a vector processing start signal. The started VPU operates to fetch the vector instruction from a main storage or a buffer storage according to the starting information and execute it. When a series of vector processing steps are terminated, the termination is noticed.
The conventional supercomputer supports only one instruction set architecture and enables to process only one program described or compiled on the basis of the supported instruction set architecture.
Of the programs executable in the supercomputer, there exist many application programs such as a library for structure calculations, and these programs take an important role. Of these programs, a lot of programs are created on the instruction set architecture for a specific vector processor. Some are provided in the form of a load module described in a machine language.
When a user of a supercomputer wants to execute an application program in a supercomputer, the program cannot be executed therein if the program is written on a different instruction set architecture from that of the supercomputer. Considering that the program is provided in the form of a source program of the FORTRAN language tuned or optimized to the instruction set architecture of a certain supercomputer, if the program is executed in a supercomputer having another instruction set architecture, high speed or performance cannot be offered. With recent prevail of several types of supercomputers, some kinds of programs have been developed on respective computers. Hence, such a situation often takes place. Further, the supercomputer has been sequentially developed up to the new systems according to the progressing pace of the hardware technology development. The new techniques unknown in developing the old systems are included in the succeeding systems. This may result in impairing the compatibility of the architecture between the new and the old systems. In such a case, the software developed on the old systems cannot be often executed in the new systems.
From a viewpoint of estimating different instruction set architectures for the old and the new systems or the software fortune, the following system is considered for processing a plurality of instruction sets in one system.
That is, to build the system for processing the different architectures, the system is configured so that the vector processors are provided for respective architectures and are closely connected to one another through a main storage. This closely-connecting technique through the main storage may use a generally available multiprocessor configuration technique.
This system, however, has so expansive a scale of the system that the system configuration may lower feasibility. In actual, hence, such a system cannot be realized. As described above, the conventional vector processor cannot process only the software program written on the instruction set architecture proper to the processor itself. This type of vector processor, therefore, cannot properly execute a program developed on the different instruction set architecture from that of another vector processor and a program developed on the old system having no architectural compatibility with the new systems.